3state HDL

module top;

initial begin
$dumpfile("a.vcd");
$dumpvars(0,top);
en=1;
repeat (10) #10 en=~en;
end
assign bd=(~en)? 3'b111 : 3'bzzz;

reg en;
wire [2:0] bd;

a a(en, bd);
endmodule

module a(en,bd);
input en;
inout [2:0] bd;
reg [2:0] r,s;
always @ (en)
if(en)
r=3'b101;
else
s=bd;
assign bd=(en)?r:1'bz;
endmodule